The present invention relates to the field of semiconductor manufacture and, more particularly, to a 2F2 flash memory.
As computers become increasingly complex, the need for improved memory storage increases. At the same time, there is a continuing drive to reduce the size of computers and memory devices. Accordingly, a goal of memory device fabrication is to increase the number of memory cells per unit area.
Memory devices contain blocks or arrays of memory cells. A memory cell stores one bit of information. Bits are commonly represented by the binary digits 0 and 1. A flash memory device is a non-volatile semiconductor memory device in which contents in a single cell or a block of memory cells are electrically programmable and may be read or written in a single operation. Flash memory devices have the characteristics of low power and fast operation making them ideal for portable devices. Flash memory is commonly used in portable devices such as laptop or notebook computers, digital audio players and personal digital assistant (PDA) devices.
In flash memory, a charged floating gate is one logic state, typically represented by the binary digit 1, while a non-charged floating gate is the opposite logic state typically represented by the binary digit 0. Charges are injected or written to a floating gate by any number of methods, including avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron injection, for example.
A memory cell or flash memory cell may be characterized in terms of its minimum feature size (F) and cell area (F2). For example, a standard NOR flash cell is typically quoted as a ten square feature cell and a standard NAND flash cell is approximately a 4.5 square feature cell. Typical DRAM (dynamic random access memory) cells are between 8 F2 and 6 F2. Cell area (F2) is determined according to a well known methodology and represents the multiple of the number of features along the x and y dimensions of a memory cell. A suitable illustration of feature size is presented in U.S. Pat. No. 6,043,562, the disclosure of which is incorporated herein by reference.
Memory devices can be created using 2-dimensional structures or using 3-dimensional structures. The 2-dimensional structures are also referred to as planar structures. Generally, 3-dimensional structures yield smaller cell sizes than planar structures. SRAMs and DRAMs have been designed using 3-dimensional structures, however few flash memory cells are fabricated using 3-dimensional structures. Most flash memory cells are fabricated using planar structures. Some flash memory cells have been fabricated using 3-dimensional structures, but they are, generally, in the size range of 4.5 F2 to 8 F2 which are not significantly smaller than flash memory cells fabricated using planar structures.
Accordingly, there is a need for a 3-dimensional flash memory device having a cell area of reduced square feature size.